1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of the Related Art
In recent years, an attention is paid to resistance change memories as subsequent candidates of flash memories. The resistive memory devices include narrowly-defined Resistive RAM (ReRAM) and Phase Change RAM (PCRAM). The Resistive RAM store resistance states in a nonvolatile manner with transition metal oxide being used as a recording layer. The Phase Change RAM use chalcogenide as a recording layer and utilize resistance information of crystalline state (conductor) and amorphous state (insulator).
Variable resistance elements of the resistive memories have two kinds of operating modes. One of them is called a bipolar type such that polarity of an applied voltage is switched and thus a high resistant state and a low resistant state are set. The other one is called as a unipolar type such that a voltage value and voltage applying time are controlled without switching the polarity of an applied voltage, and thus the high resistant state and the low resistant state can be set.
In order to realize high-density memory cell arrays, the unipolar type is preferable. This is because that the unipolar type solution enables, without transistors, cell arrays to be configured by superposing variable resistance elements and rectifier elements, such as diodes, on respective intersections between bit lines and word lines. Moreover, large capacity may be achieved without an increase in cell array area by arranging such memory cell arrays laminated in a three-dimensional manner.
Japanese Unexamined Patent Publication No. 2005-522045 describes a phase change memory with a three-dimensional memory cell, array structure in which memory cell arrays are laminated on a semiconductor substrate. In such a phase change memory device, a current flows through a selected memory cell when a bit line connected to the selected memory cell is controlled to switch from “H” level to “L” level, and a word line connected to the selected memory cell is controlled to switch from “L” level to “H” level. Write/read of the binary data is performed by detecting the current.
Most of the non-selected memory cells on the memory cell array, however, are connected to a word line and bit line different from those connected to the selected memory cell, and applied with a reverse-biased voltage, respectively. When a reverse-biased voltage is applied to a diode included in the memory cell, a leak current flows therethrough.
In addition, when plural memory cell arrays are laminated, and one of the memory cell arrays is selected therefrom, similar reverse-biased voltage may be applied to many memory cells included in non-selected memory cell arrays. This also may increase the amount of the leak current.